To lead, coordinate, and integrate the multi-disciplinary design team for the successful delivery of advanced semiconductor fabrication facilities. The Design Manager is the central point of accountability for ensuring all architectural and engineering designs are cohesive, compliant, and aligned with client requirements, project budget, and schedule. The role requires a deep understanding of semiconductor fab construction and exceptional coordination skills across all key technical disciplines.

Key Responsibilities:

1. Design Integration & Coordination:

• Act as the primary liaison between the Architectural, Mechanical (Wet & Dry), Cleanroom, and Process Utilities (Gases & Chemicals) design teams.
• Chair regular design coordination meetings to resolve conflicts, ensure spatial compatibility, and manage interfaces between disciplines.
• Oversee the development and integration of the 3D BIM (Building Information Model) using platforms like Navisworks to conduct clash detection and resolve spatial issues before construction.

2. Technical Leadership & Compliance:

• Ensure all design outputs from each discipline comply with client Technical Specification Documents (TSDs), industry standards (e.g., IBC, SEMI), and local regulations.
• Provide technical guidance to ensure design solutions for cleanrooms, process utilities, and MEP systems are constructible, safe, and aligned with project sustainability goals.
• Drive the implementation of innovative strategies such as Off-Site Manufacturing (OSM) and Digital Twin utilization across all disciplines.

3. Client & Stakeholder Management:

• Serve as a key technical point of contact for the client, facilitating collaboration on concept development and managing design-related queries.
• Coordinate with external stakeholders, including consultants, vendors, and technology providers, to ensure their requirements are accurately integrated into the design.

4. Project Delivery & Quality Assurance:

• Develop and manage the master design schedule, ensuring all deliverables from each discipline are completed on time.
• Implement and oversee a quality control process for design deliverables, managing the incorporation of design changes and ensuring document version control.
• Support the procurement and construction teams by providing technical clarifications and reviewing vendor submittals.

Professional Experience & Education:

• Bachelors degree in Architecture, Mechanical Engineering, or a related field.
• 10+ years of experience in design management, coordination, or a lead engineering role within an EPC or top-tier architectural/engineering consultancy.
• A minimum of 5 years of direct experience on semiconductor wafer fab projects is mandatory.
• Proven track record of successfully managing and integrating the following disciplines on a fast-paced, large-scale industrial project:

         o Architecture (Site planning, fab layout)
         o Mechanical Wet (UPW, Chemicals, Chilled Water)
         o Mechanical Dry (Cleanroom HVAC, Exhaust)
         o Cleanroom Engineering
         o Process Utilities (Gases & Chemicals)

Specific Skills & Knowledge:

• Expert knowledge of building codes, fab utility requirements, and cleanroom standards.
• Proficient in 3D design review tools (Navisworks, Revit) for model coordination.
• Strong financial and schedule awareness as it relates to design delivery.
• Proficient in both written and spoken English and Chinese (Mandarin) to effectively liaise with clients and other stakeholders.

Competencies:

• Strategic Integration: Ability to see the "big picture" and harmonize complex, interdependent technical systems.
• Problem-Solving: Proactive in identifying design conflicts and driving practical, timely solutions.
• Collaboration & Influence: Excellent interpersonal skills to lead a diverse, multidisciplinary team without direct authority.
• Attention to Detail: Meticulous in reviewing integrated designs and documentation.
• Leadership: Ability to motivate teams, manage stakeholder expectations, and maintain project momentum under tight deadlines.