Verification Engineer II

About X

ASIC Verification Engineer II Delft, Netherlands

CMOS

Manager

X Corporation (Nasdaq: X), a market leader in MEMS timing, offers MEMS-based silicon timing system solutions. X's configurable solutions offer a rich feature set that enables customers to differentiate their products with high performance, small size, low power, and high reliability. With over 2 billion devices shipped to date, X is changing the timing industry.

Job Summary

Develop function models for analog and mixed-signal circuit and perform full chip functional verification.

Responsibilities:

• Develop functional models for analog and mixed-signal circuits using Verilog or similar languages

• Write verification specifications based on requited test cases

• Top level digital verifications

• Develop test benches in Verilog or similar languages/environments to verify the top level

functions of full chips

• Run verification test benches and communicate results to the team for any fixes/improvements

Qualifications & Requirements:

• BA/BS Degree or higher in electrical engineering

• Experience with analog and digital circuit design

• Understanding of Analog schematic and experience with Cadence Virtuoso

• Scripting languages such as Perl / Python

• Experience with digital design languages, such as Verilog/SystemVerilog

• Strong communication skills

Desired Characteristics & Attributes:

• Excellent written and verbal communication skills required

• Understanding of mixed signal designs verification flow (modelsim/questasim)

Rev. 01

• Ability to learn new concept and tools quickly

• Ability to work well with others in a fast-paced collaborative team environment