Senior PIC Layout Engineer

Senior PIC Layout Engineer



Location: Weizmann Institute, Rehovot

Classification: Full time, on site

About the Role

We are developing a silicon-compatible photonics platform that integrates high-speed, low-energy electro-optic performance into standard silicon manufacturing. This proprietary technology targets high-bandwidth optical modulation for data centers and telecom, with future use in quantum and RF photonics.

Job Description

Join us as a senior PIC Layout & Tape-Out Engineer, one of our first hires, to own the physical implementation of the photonic integrated circuits. This hands-on role involves translating device concepts and schematics into manufacturable, testable, and scalable PIC layouts by collaborating with design, RF/electrical, packaging, test, and foundry partners.

Responsibilities:

Own the PIC layout process from concept through tape-out, including chip-level floorplanning, hierarchy, routing, verification, and final GDS preparation.

Translate specifications into manufacturable layouts for all key photonic (waveguides, couplers, modulators, photodetectors, etc.) and electrical/RF interfaces (electrodes, pads, metal routing).

Create and maintain reusable PCells and layout libraries for all photonic building blocks.

Ensure layout integrity by performing waveguide routing under optical, spacing, and design-rule constraints, and running/debugging all required signoff checks (DRC, LVS, optical connectivity, density/fill).

Prepare tape-out GDS data, support mask review, manage foundry submissions and issue resolution, and establish internal layout infrastructure and methodology (standards, checklists, version control).

Support test-chip planning, including creating structures for process monitors, calibration devices, and RF/EO testing.

Requirements:

Strong attention to detail and comfort working in an early-stage startup environment, owning problems end-to-end.

B.Sc., M.Sc., or equivalent practical experience in EE, photonics, physics, or a related field.

Hands-on experience with IC layout, and strong proficiency with Virtuoso or comparable professional layout environments.

Familiarity with foundry PDKs, design-rule manuals, GDS workflows, and tape-out preparation.

Proven ability to run and debug DRC/LVS.

Understanding of fundamental photonic layout concepts (waveguides, couplers, MZIs, etc.) and the ability to translate evolving design intent into clean, manufacturable layouts.

Experience with layout automation or scripting (Python, KLayout, gdsfactory, Luceda, or similar).

Preferred:

Prior silicon-photonics or integrated-photonics tape-out experience, especially with high-speed electro-optic PICs (modulators, photodiodes, RF pads).

Background in Analog, RF, or mixed-signal layout, particularly in Cadence Virtuoso.

Experience with advanced verification flows: photonic LVS, optical-connectivity checking, custom DRC/LVS rule decks, or non-standard foundry signoff flows.

Experience creating/maintaining PCells and familiarity with multiple foundry platforms (silicon photonics, SiN, InP, TFLN, or heterogeneous-integration).

Familiarity with MPW shuttles, full-mask tape-outs, mask review processes, and packaging-aware layout techniques (fiber attach, RF launches, thermal constraints).

Experience documenting layout methodology and enforcing design hygiene.