Digital Verification Engineer (hybrid)

Jobbex, a company that empowers people & organizations by matching great talents to great projects is looking for the next Digital Verification Engineer to help one of our clients.

Responsibilities:

• Definition and development of a Digital Verification environment using UVM and SystemVerilog.
• Define the integration of VIPs into the Digital Verification environment of the project, emphasizing standardization, development, and documentation.
• Define and formulate top-level tests for Digital Verification.
• Analyze and troubleshoot test outcomes, code coverage, and functional coverage.
• Estimate, plan, and schedule Digital Verification activities to ensure alignment with tape-out dates.

Youll be a great match if you have:

• PhD/BS/MS in Electrical Engineering with a strong foundation in Digital Verification Languages, specifically UVM and SystemVerilog. 
• Extensive experience in both RTL and Gate-Level Verification, demonstrating solid proficiency throughout the entire Digital Design Flow.
• Familiarity with Digital Verification Industry Languages (UVM, SystemVerilog) and adherence to relevant standards.
• Additional knowledge/experience in the following areas is considered a plus:
• Embedded designs and/or firmware development
• Understanding of the power management industry and applications
• Competence in I2C, I3C, SPI, USB, PMBUS
• Experience working with GITLab and expertise in Hi-speed protocols.
• Knowledge of DDR4/5 Memories.
• Effective written and verbal communication skills, coupled with a strong aptitude for teamwork and collaboration.

Enthusiastic?

Apply and lets talk!