Job Openings
Static Timing Analysis (STA) Engineer
About the job Static Timing Analysis (STA) Engineer
Job Responsibilities:
- Do working assignment for team members, tracking and supporting for critical problems.
- Co-work with IP/DFT/PD team to improve timing/area/power during synthesize.
- Netlist quality check including EQV/LowPower/Timing.
- Generate full-chip level SDC and SDC quality check.
- Responsible in synthesis, formality check, low power check and full-chip SDC generation.
Job Requirements:
- Min Diploma/Degree in related field.
- Min 3 years and above working experience in related field.
- Synthesize experience by DC/DC-NXT/Fusion-Compiler.
- EQV debug experience by FM/LEC.
- Low power check experience by VC-LP.
- Static Timing Analysis experience by PT.
- Power Analysis experience by PTPX.
- Good at scripts, like Python/perl/Tcl/Shell.
- Proficiency in English, Bahasa Melayu and Mandarin because will need to communicate with client from China.
- Will work in big and complex with advanced process and technology.
- Knowledgeable in all aspects of ASIC design flow.
- Familiar with EDA tools.
- Good leadership skills.
- Good teamwork and script skills.
- Good training skills to ramp-up new team members.